1. Field of the Invention
The present invention relates, in general, to a semiconductor device and, more particularly, to a CMOS device which is remarkably reduced in the area of the element isolation region between an N well and P well and in the area of the substrate electrode. Also, the present invention is concerned with a method for fabricating the semiconductor device.
2. Description of the Prior Art
Generally, a semiconductor device consisting of a transistor and a capacitor generally forms one independent element in an integrated circuit and so it requires an element isolation region between active regions to prevent the elements from interfering with one another in their operations.
The recent trend of high integration of semiconductor devices has compelled many efforts to reduce the element isolation region, which generally occupies much area in a semiconductor device. Many processes for this purpose have been developed. Representative are a local oxidation of silicon (LOCOS) process and a selective polysilicon oxidation (SEPOX) process. In the LOCOS process, an element isolation oxide film is formed by thermal oxidation of a semiconductor substrate in the presence of a mask of nitride film pattern that locally exposes the semiconductor substrate. Likewise, the SEPOX process comprises thermal oxidation of a semiconductor substrate in the presence of a mask consisting of a combination of polysilicon film and nitride film pattern that locally exposes the semiconductor substrate. Apart from these processes, there is a process in which a trench is formed by selective etch of a semiconductor substrate and then filled with an insulating material, so as to form a trench element isolation oxide film. Of the above-illustrated processes, the LOCOS process is most widely used because of its relative simplicity.
In order to better understand the background of the invention, a description of the LOCOS process will be given. To begin with, the surface of a silicon semiconductor substrate is thermally oxidized to grow a pad oxide film. Then, a nitride film pattern is formed on the pad oxide film, to expose a predetermined area of the semiconductor substrate which is destined to be an element isolation region. Finally, another thermal oxidation is applied to the semiconductor substrate to grow a field oxide film with the nitride pattern serving as a mask.
However, this LOCOS process has a problem known as bird's beak wherein the field oxide film encroaches the active region, resulting in a reduction in the area of the active region. In addition, when a subsequent exposure process is carried out in order to form a photosensitive film pattern, light is reflected from the slanted surface of the bird's beak, so as to illuminate the photosensitive film undesirably. As a result, the problem of notching is generated. These problems cause degradation of production yield and reliability when a gate poly is patterned in a semiconductor device under the design rule of 0.4 .mu.m or less.
Referring to FIG. 1, there is a circuit diagram showing a typical CMOS device comprising an N type MOSFET and a P type MOSFET which are connected to each other. As shown in FIG. 1, the source electrodes (S) of the PMOS and NMOS are connected with V.sub.DD and V.sub.SS, respectively, and the drain electrodes (D)2 thereof are connected to each other.
With reference to FIG. 2, there is a layout of main masks in which an N well mask 1, active masks 2, a gate mask 3, contact hole masks 4, and wiring masks 5 are conventionally arranged to fabricate the circuit of FIG. 1.
FIG. 3 shows a semiconductor device fabricated by the conventional technique taken through line I--I of FIG. 2. Its fabrication processes starts with the formation of a P well 12 and an N well in predetermined areas of a P type semiconductor substrate 11 by use of a P well mask (not shown) and the N well mask 1, respectively. Then, element isolation films 14 are formed at the boundary between the two wells and at predetermined areas of the wells. A gate oxide film 15 is formed over each well, followed by the formation of a gate electrode 16 over the gate oxide film by use of the gate mask 3. While this gate structure serves as a mask, N type impurities are implanted into the P well 12 whereas P type impurities are implanted into the N well 13. As a result, a set of source electrodes 17 and drain electrodes 18 is established in each well. A voltage of V.sub.SS is applied to the P type semiconductor substrate 11. In order to supply a voltage of V.sub.DD for the N well 13, a substrate electrode 19 is established by implanting N type impurities into a region which is separated by the source electrode 17A and the element isolation oxide film 14 in the N well 13. Thereafter, a blanket interlayer insulting film is coated over such MOSFET structures. This blanket film is patterned by an etch process using the contact hole masks 4, to form a pattern of interlayer insulating film 21 containing contact holes 20 through which the source electrodes 17A, 17B and drain electrodes 18A, 18B and the substrate electrode 19 are exposed. The wiring masks 5 are used to form three wirings 22. One is to connect the source electrode 17A and substrate electrode 19 of P-MOSFET with V.sub.DD, another for connection between the drain electrode 18A of P-MOSFET and the drain electrode 18B of N-MOSFET, and the other for the source electrode 17B of N-MOSFET and V.sub.SS.
As previously mentioned, the element isolation oxide film for isolating the N-MOSFET from the P-MOSFET, if fabricated by LOCOS, occupies much area. The above-illustrated conventional technique has another difficulty in achieving high integration of a semiconductor device because the additionally formed substrate electrode is separated from the source electrode of the P-MOSFET by the element isolation oxide film, which leads to consumption of too much area.